BSC Coordinates Development of RISC-V 'Lagarto' Processor

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Computer architecture

Instruction set architectures

Computing

Embedded microprocessors

Microprocessors

Central processing unit

Classes of computers

Microcontrollers

RISC-V

Reduced instruction set computer

Open-source hardware

Mateo Valero

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BSC Coordinates Development of RISC-V 'Lagarto' Processor. View article details on hiswai:

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<div>Jan. 6, 2019 — Lagarto, which is built with <b>TSMC's</b> 65-nanometer transistors, is the first open source instruction set architecture (ISA) chip developed ...</div>

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