Cadence Prototypes First IP Interface in Silicon for Preliminary Version of DDR5 Standard Being ...

Excerpt

<div>The Cadence test chip was fabricated in <b>TSMC's</b> 7nm process and achieves a 4400 megatransfers per second (MT/sec) data rate, which is 37.5 percent faster than the fastest commercial DDR4 memory at 3200MT/sec. With this key milestone, SoC providers developing high-speed memory subsystems ...</div>